A throughput (e.g., a rate of a successful message delivery over a communication channel measured by data bits per second) loss may occur in an integrated circuit (e.g., a semiconductor integrated circuit, silicon chip, etc.). Throughput loss may be the result of an architectural constraint and/or a design limitation within the integrated circuit itself. A designer of the integrated circuit may use a process to detect the throughput loss in order to validate network architecture.
The process may include detecting a particular transmission line (e.g., a computer bus, a subsystem that transfers data between computer components) in the integrated circuit that may not be providing an expected throughput. However, the process may not detect a location in the particular transmission line of a deficiency in the throughput occurred. It may be an additional task for the user (e.g., designer, chip architect, system developer, etc.) to determine the location and/or a cause of a throughput deficiency. The additional task may be a time consuming and/or increase the cost of designing the integrated circuit.